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Philips Semiconductors
PCF8582C-2
256 × 8-bit CMOS EEPROM with I 2 C-bus interface
Table 7: Characteristics …continued
V DD = 2.5 to 6.0 V; V SS = 0 V; T amb = ? 40 to +85 ° C; unless otherwise speci?ed.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SDA input/output (pin 5)
V IL
V IH
LOW level input voltage
HIGH level input voltage
? 0.8
0.7V DD
-
-
0.3V DD
+6.5
V
V
V OL
I LO
C i
LOW level output voltage
output leakage current
input capacitance
I OL = 3 mA; V DD(min)
V OH = V DD
V I = V SS
-
-
-
-
-
-
0.4
1
7
V
μ A
pF
Data retention time
t S
data retention time
T amb = 55 ° C
10
?
?
years
11. I 2 C-bus characteristics
Table 8: I 2 C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V IL and V IH
with an input voltage swing from V SS to V DD ; see Figure 9 .
Symbol
f SCL
t BUF
Parameter
clock frequency
bus free time between a STOP and
Conditions
Min
0
4.7
Max
100
?
Unit
kHz
μ s
START condition
t HD;STA
START condition hold time after
4.0
?
μ s
which ?rst clock pulse is generated
t LOW
t HIGH
LOW level clock period
HIGH level clock period
4.7
4.0
?
?
μ s
μ s
t SU;STA
set-up time for START condition
repeated start
4.7
?
μ s
t HD;DAT
data hold time
for bus compatible masters
5
?
μ s
for bus devices
[1]
0
?
ns
t SU;DAT
t r
t f
t SU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250
?
?
4.0
?
1
300
?
ns
μ s
ns
μ s
[1]
The hold time required (not greater than 300 ns) to bridge the unde?ned region of the falling edge of SCL must be internally provided by
a transmitter.
9397 750 14222
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 25 October 2004
11 of 21
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